1. Field of the Invention
The present invention relates to a system-on-chip (SoC)-based system network protocol in consideration of network efficiency, and more particularly, to a network protocol for data exchange in a chip-based system.
2. Discussion of Related Art
In recent years, with the development of semiconductor process technology and system design technology, SoC technology has developed rapidly. As methods and technologies of building a system become diversified, an internal structure of an SoC becomes more complicated. Also, as a variety of high-quality multimedia data are required, an amount of data to be processed has tremendously increased. To this end, multiple processors for parallel processing are embedded and intellectual properties (IPs) for various communication and peripheral devices are included to realize various functions, leading to a system including several chipsets, and research is being conducted for introduction of a network-on-chip (NoC) for parallel processing, making communication inside the system very complex. Accordingly, system performance is greatly affected by data communication performance rather than computing power of a computing unit. To resolve such problems, a variety of on-chip-network structures and protocols have been studied.
AMBA AHB, AMBA AXI, WISHBONE, CoreConnect, OCP, SNP, XSNP and the like are representative interface protocols. Representative on-chip-network structures include Nostrum, Hermes, QNOC, aSoC, Octagon, AEthereal, SoCBus, SNA, AMBA interconnect matrix, AXI Interconnect, Smart Interconnect and the like.
In the case of on-chip protocols, protocols for communication inside the SoC described above are less compatible with protocols for communication of an NoC such as Nostrum or off-chip communication such as PCI express. Accordingly, it is not suitable to use such protocols as NoC or off-chip protocols. A protocol including a number of control signal lines is not suitable for off-chip communication with a narrow data width. Recently, as design of a processor having multiple cores has become active, commercial technologies that can be variously applied to off-chip communication, such as processor-to-processor connections or chip-to-chip connections, are being developed. Such a trend of design requires high-performance off-chip communication as on-chip communication and off-chip communication are seamlessly connected.
In the number of signal lines, the off-chip communication is more limited than the on-chip communication. Since the number of interface signal lines is directly associated with the number of input/output pins of a package and the number of lines of a printed circuit board (PCB), the number of interface signal lines is sensitive to physical cost and an operating frequency. Accordingly, three or more types of protocols may be present in a multi-chipset including an NoC. This makes system design complex and causes performance degradation due to protocol conversion in communication.
Meanwhile, most of the existing interface protocols are asymmetric protocols and have a format in which communication is initiated by a master and terminated by a slave. Accordingly, a bidirectional protocol requiring an immediate response, such as AHB, is inefficient since a communication channel is open until the communication is completed. Also, in a point-to-point communication-based protocol such as AXI, a master needs to re-initiate communication using an interrupt or polling scheme in order to receive a result of execution from the slave after delivering a command even when a communication channel need not be opened due to the protocol supporting unidirectional communication.
To resolve this problem, an existing protocol allows an IP to have both a master interface and a slave interface to improve performance. However, double signal lines are required in order for one IP to have two such functions due to an asymmetric structure between the master interface and the slave interface. Also, there are many protocols including many signal lines to provide various functions in transferring data and improve performance. When a scale of the SoC is increased and many functional blocks are integrated into one system, a number of signal lines may cause routing congestion. Accordingly, there is a need for technology by which desired effects can be obtained while minimizing the number of additional signal lines.
As there are a variety of communication patterns of an SoC system, a differentiated service that supports quality of service (QoS) is provided on an on-chip network, as in a computer network. In most existing network structures, QoS is determined in the on-chip network, and an opportunity to select QoS is not provided to an IP that performs actual communication. This is because the existing on-chip network structure is used only for a specific system or provides only structural support with no consideration of characteristics of a variety of systems. Also, since the existing protocol has no consideration for QoS support, an IP designer cannot implement an IP to selectively generate QoS depending on conditions. Recently, a QoS signal has been added in AMBA AXI4, but use of the QoS signal has not been sufficiently studied and functions of the QoS signal have not been clearly defined. In a structure in which various communication traffics may be generated due to parallel processing like a multi-processor SoC (MPSoC), if QoS can be determined on an IP level, more efficient communication can be performed.